1. Field of the Invention
The present invention relates to semiconductor device processing. More particularly, the present invention relates to an anti-reflective coating used in connection with photolithography in semiconductor device processing.
2. Discussion of the Related Art
Use of an anti-reflective coating in photolithographic processing of semiconductor devices is described, for example, in U.S. Pat. No. 5,710,067 by Foote et al., issued Jan. 20, 1998. By suppressing multiple reflections and interferences that otherwise produce diffusely and nonuniformly illuminated lithographic exposure, an anti-reflective coating permits sharper and higher resolution lithographic exposure and patterning, thus allowing higher device densities to be achieved. An anti-reflective coating can be applied, for example, in photolithographically forming contacts and vias to gate electrodes.
A conventional anti-reflective coating for photolithography includes various inorganic and organic materials, such as amorphous silicon, silicon nitride, silicon oxynitride, xcex1-carbon, titanium nitride, silicon carbide, silicon oxide, spin-on polyimides and polysulfones. Typically, a single-layer anti-reflective coating is used, although multilayer coatings offer predicted superior performance. A multilayer coating, however, presents complexities in deposition and removal, which can result in trace contaminants (e.g., nitrogen poisoning) that degrade device performance.
FIG. 1A is a split cross-sectional schematic diagram of a conventional semiconductor device structure 100. In the left hand portion of FIG. 1A, an oxide layer 104 is formed, typically using LOCOS technology, at a principal surface 106 of a semiconductor substrate 102. Overlying oxide layer 104 is typically deposited an electrically conductive layer 110. Deposited overlying conductive layer 110 is typically a dielectric layer 112. A conventional anti-reflective coating 114, containing, for example, silicon nitride, is then deposited overlying dielectric layer 112. A photoresist layer 120 is deposited over conventional anti-reflective coating 114.
The right hand portion of FIG. 1A shows semiconductor device 100 at a later stage of processing than that shown in the left hand portion of FIG. 1A. Photoresist layer 120 is selectively exposed and patterned. Anti-reflective coating 114 suppresses multiple reflections and interferences, enabling sharp edge resolution at the boundaries between exposed and unexposed portions of photoresist layer 120. Exposed portions of dielectric layer 112 are then etched through patterned photoresist layer 120, exposing a portion of the surface of electrically conductive layer 110 and substantially preserving the sharp edge resolution established between exposed and unexposed portions of photoresist layer 120.
FIG. 1B is a split cross-sectional schematic diagram of semiconductor device 100 at a later processing stage than that shown in FIG. 1A. After removal of excess photoresist 120, as shown in the left hand portion of FIG. 1B, an electrically conductive structure 122 is formed overlying the exposed surface of electrically conductive layer 110 within the cavity etched into dielectric layer 112. Subsequent processing steps, e.g., formation of an electrically conductive layer 124 overlying dielectric layer 112, typically require prior removal of any residual traces of anti-reflective coating 114, as shown in the right hand portion of FIG. 1B.
In accordance with the present invention, a multilayer electrically conductive stack is formed over a surface in a semiconductor device prior to a photolithographical step. Alternate layers of the stack, having chemical and electrical characteristics similar to those of an underlying device structure, contain materials that differ in their refractive indices. A photoresist layer is deposited over the multilayer anti-reflective stack, and patterned. During an exposure step in the patterning, the multilayer anti-reflective stack effectively suppresses multiple reflections and interferences from an underlying structure in the semiconductor device, thus providing sharpened edge resolution in the patterning. Consequently, high device density can be achieved.
Because the multilayer anti-reflective stack has chemical and electrical compatibility with an adjacent conductive material of the semiconductor device, removal of the remaining multilayer stack after the photolithographical step is not required. Therefore the multilayer stack advantageously remains in place during subsequent processing steps and in the final device, where it forms all or a part of an electrically conductive device structure (e.g., a gate or an interconnect structure).
In an embodiment of the invention, alternate layers of Si1xe2x88x92xGex and Si can be provided as a multilayer stack (e.g., 2 to 10 layers).